Memory devices generally comprise a plurality of gate structures. These gate structures may include a control gate and a floating gate that is positioned between the control gate and a substrate. The floating gate is a conductive layer normally fabricated of a polysilicon material. The floating gate is not attached to any electrodes or power sources and is itself generally surrounded by an insulation material.
The operation of the memory cells is dependent upon the charge stored in the floating gate at the threshold voltage needed to represent information stored in these devices. Performance of the memory cells typically includes a performance specification or rating of the programming speed that influences the speed of erase and write operations. The speed is typically limited by the rate at which electrons can be pumped into (writing) and out of (erasing) the device without causing damage to the device. Typically, erasing and writing operations must be capable of operating within 1 msec at a specified applied voltage.
The semiconductor industry is increasingly driven towards smaller and more capable electronic devices, such as smaller memory devices. To reduce the size of such devices, while maintaining or improving their respective capabilities, the size of components and the distance between such components may be reduced.
Applicant has identified deficiencies and problems associated with conventional processes for manufacturing memory devices and the resulting memory devices. For instance, with regards to flash memory devices, as the cell size is reduced, issues arise that prevent further reduction in size while maintaining the cell's capabilities and respective function. As the individual layers of the gate structures are made smaller and moved closer to each other, charge leakage from the floating gate may increase, thereby reducing performance of the device.
Through applied effort, ingenuity, and innovation, certain of these identified problems have been solved by developing solutions that are included in various embodiments of the present invention, which are described in detail below.